Help:Make
Make is a standard unix tool that automatically builds projects using dependency based instructions. Any process that requires repeated commands to create or update files from other files can be automated with a makefile.
- Software availability
- all unix systems, most windows compilers
- Other related software
- C compiler, gcc
- command to type to run
- make
- View online documentation
- man make
- info make (for gnu make)
Additional notes[edit]
This is a quick tutorial for make -- please read the man page or info pages for more complete documentation.
Syntax[edit]
Make reads its instructions from a file called Makefile (or several other default variations) in the current directory. This file is line based, and contains the following types of lines:
- comment lines and blank lines
- Any line starting with a # character is a comment line
- value lines
- of the form VARIABLE=value (variables can also be set on the make command line)
- dependency lines
- of the form target: dep1 dep2 dep3...
- This means that target relies on the listed dependencies to be built. If any of them are newer than target, then the following rule line is used to rebuild target.
- rule line
- One or more rule lines follow a dependency. Rule lines must start with a tab character. These lines are run by the shell to build the target.
Variables can be substituted anywhere with the syntax ${VARIABLE}
Shell variables (e.g., $i) must double the dollarsign character (e.g., $$i) to prevent make from using it as a make variable.
Predefined and standard variables[edit]
Different variations of make may define slightly different variables. These variables are used by implicit rules. Some have default values.
- CC
- default C compiler
- CFLAGS
- options for the C compiler
- LDFLAGS
- compiler options for linking
- CPPFLAGS
- preprocessor options for compiling
- FC
- default fortran compiler
- FFLAGS
- options for the fortran compiler
Examples[edit]
TARGETS=myprogram anotherprogram
CFLAGS=-O2
CC=gcc
SCRATCH=*.o core *~ *.bak
all: $(TARGETS)
clean:
rm -f $(SCRATCH)
clobber: clean
rm -f $(TARGETS)
myprogram: myprogram.c
$(CC) $(CFLAGS) -o myprogram myprogram.c
anotherprogram: anotherprogram.o morestuff.o
gcc -O2 -o anotherprogram anotherprogram.o morestuff.o
(If you copy and paste the above, replace spaces at the start of the line with a tab.)
Note that both of the compile rules above are redundant, as make's implicit rules will know how to automatically build targets with rules that simple. Each variation of make has slightly different implicit rules; check the specific documentation for a list of these.
If you type type make it will try to build the first target (all). If you want to build something different, supply a list of targets on the command line (e.g., make anotherprogram).
The purpose for these rules is:
- all
- build all targets
- clean
- clean up all intermediate files and scratch files, but leave the final executables
- clobber
- clean up everything including executables, leaving only source files
- myprogram
- This target has a single source file, and will compile directly to an executable.
- anotherprogram
- This target uses multiple object files to build the executable. Make's implicit rules will be used to create the object files from source files which must exist but don't need to be listed in the makefile.